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PRELIMINARY
AM79761
Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHYTM-SD)
DISTINCTIVE CHARACTERISTICS
n Gigabit Ethernet Transceiver operates at 1.25 Gigabits per second (Gbps) n Suitable for both Coaxial and Optical Link applications n 10-bit TTL Interface for Transmit and Receive Data n Monolithic Clock Synthesis and Clock Recovery requires no external components n Word Synchronization Function (Comma Detect) n Low Power Operation - 700 mW typical n 64-pin Standard PQFP -- 14 x 14 mm (0 C - 70 C) -- 10 x 10 mm (0 C - 50 C) n 125 MHz TTL Reference Clock n Loopback Diagnostic n Single +3.3 V Supply
GENERAL DESCRIPTION
The AM79761 Gigabit Ethernet Physical Layer Serializer/Deserializer (GigaPHY-SD) device is a 1.25 Gbps Ethernet Transceiver optimized for Gigabit Ethernet/ 1000BASE-X applications. It implements the Physical Medium Attachment (PMA) layer for a single port. The GigaPHY-SD device can interface to fiber-optic media to support 1000BASE-LX and 1000BASE-SX applications and can interface to copper coax to support 1000BASE-CX applications. The functions performed by the device include serializing the 8B/10B 10-bit data for transmission, deserializing received code groups, recovering the clock from the incoming data stream, and word synchronization. When transmitting, the GigaPHY-SD device receives 10-bit 8B/10B code groups at 125 million code groups per second. It then serializes the parallel data stream, adding a reference clock, and transmits it through the PECL drivers. When receiving, the GigaPHY-SD device receives the PECL data stream from the network. It then recovers the clock from the data stream, deserializes the data stream into a 10-bit code group, and transmits it to the Physical Coding Sublayer (PCS) logic above. Optionally, it detects comma characters used to align the incoming word.
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 21560 Rev: A Amendment/+1 Issue Date: April 1998
PRELIMINARY
BLOCK DIAGRAM
10 DQ Parallel to Serial TX+ TX-
TXD[0:9]
REFCLK EWRAP RXD[0:9] 10 QD
PLL Clock Multiply
Serial to Parallel 10
Clock Recovery
RX+ RX-
RCLK 20 RCLKN Comma Detect
21560A-1
COM_DET EN_CDET
Frame Logic
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AM79761
PRELIMINARY
CONNECTION DIAGRAM
N/C DVDD_P TX+ TXDVDD_P DVDD AVSS AVDD DVSS DVDD RX+ DVDD_P RXDVSS DVDD N/C 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DVSS TXD0 TXD1 TXD2 DVDD TXD3 TXD4 TXD5 TXD6 DVDD TXD7 TXD8 TXD9 DVSS DVSS N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
N/C COM_DET DVSS_T RXD0 RXD1 RXD2 DVDD_T RXD3 RXD4 RXD5 RXD6 DVDD_T RXD7 RXD8 RXD9 DVSS_T
N/C TEST1 EWRAP TEST2 DVSS REFCLK TEST3 EN_CDET DVSS TEST4 N/C DVDD DVDD_T RCLKN RCLK DVSS_T
21560A-2
Note: N/C = No Connect
LOGIC SYMBOL
DVDD REFCLK RCLK RCLKN EN_CDET EWRAP COM_DET
DVDD_T
DVDD_P
AVDD TXD [0:9] RXD [0:9] To PCS
PHY Control
AM79761 GigaPHY-SD Test Port TEST4 TDST [3:1]
TX+ TX- RX+ RX-
Transceiver
DVSS
DVSS_D
DVSS
21560A-3
AM79761
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PRELIMINARY
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. AM79761 Y C -10
PACKAGE SIZE OPTION -10 = 10 x 10 mm body size -14 = 14 x 14 mm body size TEMPERATURE RANGE C = Commercial (0C to +70C) PACKAGE TYPE Y = 64-Pin Plastic Quad Flat Pack (PDH064)
DEVICE NUMBER/DESCRIPTION AM79761 Physical Layer 10-Bit Transceiver for Gigabit Ethernet GigaPHYTM-SD)
Valid Combinations AM79761YC AM79761YC -10 -14
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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AM79761
PRELIMINARY
RELATED PRODUCTS
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Description Local Area Network Controller for Ethernet (LANCE) Serial Interface Adapter (SIA) IEEE 802.3/Ethernet/Cheapernet Transceiver CMOS Local Area Network Controller for Ethernet (C-LANCE) Twisted Pair Ethernet Transceiver (TPEX) Twisted Pair Ethernet Transceiver Plus (TPEX+) Quad Fast Ethernet Transceiver for 100BASE-X Repeaters (QFEXrTM) Integrated Multiport Repeater Plus (IMR+TM) basic Integrated Multiport Repeater (bIMRTM) Integrated Multiport Repeater 2 (IMR2TM) enhanced Integrated Multiport Repeater (eIMRTM) enhanced Integrated Multiport Repeater Plus (eIMR+TM) Hardware Implemented Management Information Base (HIMIBTM) Quad Integrated Ethernet Transceiver (QuIETTM) Integrated Local Area Communications Controller (ILACCTM) Media Access Controller for Ethernet (MACETM) PCnetTM-ISA Single-Chip Ethernet Controller (for ISA bus) PCnetTM-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft(R) Plug n' Play(R) Support) PCnetTM-ISA II Full Duplex Single-Chip Ethernet Controller for ISA PCnetTM-32 Single-Chip 32-Bit Ethernet Controller PCnetTM-PCI Single-Chip Ethernet Controller (for PCI bus) PCnetTM-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus) PCnetTM-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
AM79761
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PRELIMINARY
PIN DESIGNATION Listed by Pin Number
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name DVSS TXD0 TXD1 TXD2 DVDD TXD3 TXD4 TXD5 TXD6 DVDD TXD7 TXD8 TXD9 DVSS DVSS N/C Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name N/C TEST1 EWRAP TEST2 DVSS REFCLK TEST3 EN_CDET DVSS TEST4 N/C DVDD DVDD_T RCLKN RCLK DVSS_T Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name DVSS_T RXD9 RXD8 RXD7 DVDD_T RXD6 RXD5 RXD4 RXD3 DVDD_T RXD2 RXD1 RXD0 DVSS_T COM_DET N/C Pin No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name N/C DVDD DVSS RXDVDD_P RX+ DVDD DVSS AVDD AVSS DVDD DVDD_P TXTX+ DVDD_P N/C
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AM79761
PRELIMINARY
PIN DESCRIPTION
TX+, TXSerial Transmit Data PECL Output These pins are the 1000BASE-X port differential drivers which transmit the serial stream to the network. These pins are connected to the copper or fiber optic connectors. When EWRAP is LOW, the pins assume normal operation. When HIGH, TX+ is logic HIGH and TX- is logic LOW. RX+, RXSerial Receive Data PECL Input These pins are the 1000BASE-X port differential receiver pair, receiving a serial stream of data from the network. These pins are connected to the copper or fiber optic connectors. When EWRAP is LOW, the pins assume normal operation. The pins are internally biased. TXD[0:9] Transmit Data TTL Input The TXD[0:9] pin is a set of 10 data signals which are driven from the Physical Coding Sublayer (PCS) above. The 10 bits of data are clocked in parallel on the rising edge of REFCLK. TXD0 is transmitted first on TX. RXD[0:9] Receive Data TTL Output The RXD[0:9] pin is a set of 10 data signals which are sent to the Physical Coding Sublayer (PCS) above. The 10 bits of data are clocked out in parallel on the rising edges of RCLK and RCLKN. RXD0 is received first on RX. REFCLK Reference Clock TTL Input This input is used for the 125-Mhz clock. The rising edge of this clock latches TXD[0:9] into an input register. This clock serves as the reference clock at 1/10th the baud rate for the PLL. RCLK, RCLKN Receive Clock TTL Output These pins provide the differential receive clock signals, derived from the RX data stream, and are at 1/20th the baud rate of the receive stream. Parallel data on RXD[0:9] is provided at each rising transition of RCLK and RCLKN. EN_CDET Enable Comma Detect TTL Input This pin is used to enable the word synchronization mode. When logic HIGH, the COM_DET output is enabled and word synchronization is active. COM_DET Comma Detect Indicator TTL Output Comma Detect is asserted to indicate that the incoming word on RXD[0:9] contains a Comma character (0011111xxx). COM_DET goes HIGH for half of a RCLK period, and can be captured when RCKLN is rising. In order for COM_DET to provide indication, EN_CDET must be enabled (logic HIGH). EWRAP Loopback Enable TTL Input When EWRAP is asserted, the transmitted data stream is sent back to the receiver through an internal loopback path. TX+ is logic HIGH, and TX- is logic LOW in this mode. This pin is logic LOW for normal operation. TEST[1:3] Factory Test Pins Input These pins should be tied to DVDD for normal operation. TEST[4] Factory Test Pin Output This pin should be left unconnected for normal operation. DVDD Power These pins supply power to the digital blocks of the device. They must be connected to a 3.3 V 5% source. DVDD_T TTL Power These pins supply power to the TTL blocks of the device. They must be connected to a 3.3 V 5% source. DVDD_P PECL Power These pins supply power to the PECL blocks of the device. They must be connected to a 3.3 V 5% source. It is critical that the signal supplied to these pins are clean to ensure good performance of the device.
AM79761
7
PRELIMINARY AVDD Analog Power These pins supply power to the analog blocks of the device. They must be connected to a 3m.3 V 5% source and require careful decoupling to ensure proper device performance. DVSS Ground These pins are the ground connections for the digital blocks. They must be connected to the common external ground plane. DVSS_T Ground These pins are the ground connections for the TTL blocks. They must be connected to the common external ground plane. AVSS Ground These pins are the ground connections for the analog blocks. They must be connected to an analog ground plane.
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AM79761
PRELIMINARY
FUNCTIONAL DESCRIPTION Overview
The GigaPHY-SD device provides the PMA functionality for 1000BASE-X systems. The GigiaPHY-SD communicates with the PCS through the 10-bit code groups and communicates with the Physical Medium Dependent (PMD) layer to transmit and receive data from the network, through either fiber optic or copper coax media. The GigaPHY-SD device consists of the following functional blocks: n 1000BASE-X Transmit block including: -- Clock Synthesizer -- Serializer and Transmission interface n 1000BASE-X Receive block including: -- Clock Recovery -- Deserializer -- Word Alignment and synchronization
Clock Synthesizer
The AM79761 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to achieve a baud rate clock at nominally 1.25 GHz. The clock synthesizer contains a fully monolithic PLL which does not require any external components.
Serializer
The AM79761 device accepts TTL input data as a parallel 10-bit character on the TXD[0:9] bus which is latched into the input latch on the rising edge of REFCLK. This data will be serialized and transmitted on the TX PECL differential outputs at a baud rate of ten times the frequency of the REFCLK input, with bit TXD0 transmitted first. User data should be encoded for transmission using the 8B/10B block code described in the IEEE 802.3 specification.
Transmission Character Interface
An encoded byte is 10 bits and is referred to as a transmission character. The 10-bit interface on the AM79761 device corresponds to a transmission character. This mapping is shown in Table 20.
Table 20.
Transmission Order and Mapping of an 8B/10B Character
Parallel Data Bits 8B/10B Bit Position Comma Character
T9 j X
T8 h X
T7 g X
T6 f 1
T5 i 1
T4 e 1
T3 d 1
T2 c 1
T1 b 0
T0 a 0
Last Data Bit Transmitted
First Data Bit Transmitted
Clock Recovery
The AM79761 device accepts differential high speed serial inputs on the RX pins, extracts the clock and retimes the data. The AM79761 clock recovery circuitry is completely monolithic and requires no external components. For proper operation, the baud rate of the data stream to be recovered should be within 0.01% of ten times the REFCLK frequency. For example, if the REFCLK used is 125 MHz, then the incoming serial baud rate must be 1.25 gigabaud 0.01 percent.
downstream controller chip. The clocks are generated by dividing down the high-speed clock which is phase locked to the serial data. The serial data is re-timed by the internal high-speed clock and deserialized. The resulting parallel data will be captured by the adjoining protocol logic on the rising edges of RCLK and RCLKN. In order to maximize the setup and hold times available at this interface, the parallel data is loaded into the output register at a point nominally midway between the transition edges of RCLK and RCLKN. If serial input data is not present or does not meet the required baud rate, the AM79761 will continue to produce a recovered clock so that downstream logic may continue to function. The RCLK and RCLKN output frequency under these circumstances may differ from their expected frequency by no more than 1 percent.
Deserializer
The re-timed serial bit stream is converted into a 10-bit parallel output character. The AM79761 device provides complementary TTL recovered clocks, RCLK and RCLKN, which are at 1/20th of the serial baud rate. This architecture is designed to simplify demultiplexing of the 10-bit data characters into a 20-bit half-word in the
AM79761
9
PRELIMINARY
Word Alignment
The AM79761 device provides 7-bit comma character recognition and data word alignment. Word synchronization is enabled by asserting EN_CDET HIGH. When synchronization is enabled, the AM79761 device constantly examines the serial data for the presence of the Comma character. This pattern is 0011111XXX, where the leading zero corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5, and K28.7, which are defined specifically for synchronization purposes. Improper alignment of the comma character is defined as any of the following conditions: 1. The comma is not aligned within the 10-bit transmission character such that TXD0...TXD6 = "0011111." 2. The comma straddles the boundary between two 10-bit transmission characters. 3. The comma is properly aligned but occurs in the received character presented during the rising edge of RCLK rather than RCLKN. When EN_CDET is HIGH and an improperly aligned comma is encountered, the internal data is shifted in such a manner that the comma character is aligned
properly in RXD[0:9]. This results in proper character and half-word alignment. When the parallel data alignment changes in response to an improperly aligned comma pattern, some data which would have been presented on the parallel output port may be lost. However, the synchronization character and subsequent data will be output correctly and properly aligned. When EN_CDET is LOW, the current alignment of the serial data is maintained indefinitely, regardless of data pattern. When encountering a comma character, COM_DET is driven HIGH to inform the user that realignment of the parallel data field may have occurred. The COM_DET pulse is presented simultaneously with the comma character and has a duration equal to the data, or half of an RCLK period. The COM_DET signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of RCLKN. Functional waveforms for synchronization are given in Figure 18 and Figure 19. Figure 18 shows the case when a comma character is detected and no phase adjustment is necessary. It illustrates the position of the COM_DET pulse in relation to the comma character on RXD[0:9]. Figure 19 shows the case where K28.5 is detected, but it is out of phase and a change in the output data alignment is required. Note that up to three characters prior to the comma character may be corrupted by the realignment process.
RCLK
RCLKN
COM_DET
RXD[0:9]
K28.5
TChar
TChar
TChar
Note : TChar = 10-bit Transmission Character
21560A-4
Figure 18.
Detection of a Properly Aligned Comma Character
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AM79761
PRELIMINARY
RCLK
RCLKN
COM_DET
RXD[0:9] Potentially Corrupted
K28.5
TChar
TChar
TChar
K28.5
TChar
21560A-5
Figure 19.
Receiving Two Consecutive K28.5 + TCharacter Transmission Words
AM79761
11
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . .-65 C to +150 C Ambient Temperature Under Bias . .-55 C to +125 C Power Supply Voltage (VDD) . . . . . . . -0.5 V to +4.0 V DC Voltage (PECL Inputs) . . . . . .-0.5 V to VDD +0.5 V DC Voltage (TTL Inputs). . . . . . . . . . . -0.5 V to +5.5 V Output Current (TTL Outputs) . . . . . . . . . . . . -50 mA Output Current (PECL Outputs) . . . . . . . . . . . -50 mA Maximum Input ESD (Human Body Model) . . . 1500 V
OPERATING RANGES
Temperature (TA) 0 C to +70 C for 14 x 14 mm PQFP . . . . . . . . . . . . . 0 C to +50 C for 10 x 10 mm PQFP Power Supply Voltage (DVDD) . . . . . . . . . +3.3 V 5%
Operating ranges define those limits between which functionality of the device is guaranteed.
Stresses above those listed under Absolute Maximum Ratings may cause per manent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
DC CHARACTERISTICS (over recommended operating conditions)
Symbol VIH VIL IIH IIL VOH VOL VOUT75 VOUT50 VIN IDD PD Parameter Description Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Output HIGH voltage (TTL) Output LOW voltage (TTL) TX Output differential peak-topeak voltage swing TX Output differential peak-topeak voltage swing Receiver differential peak-topeak Input Sensitivity RX Supply Current Power dissipation VIN =2.4 V VIN =0.5 V IOH = -1.0 mA IOL = +1.0 mA 75 to VDD - 2.0 V 50 to VDD - 2.0 V Internally biased to VDD/2 Outputs open, VDD = VDD max Outputs open, VDD = VDD max Test Conditions Min 2.0 0 -- -- 2.4 -- 1200 1200 400 -- -- Typ -- -- 50 -- -- -- -- -- -- 210 700 Max 5.5 0.8 500 -500 -- 0.5 2200 2200 3200 290 1000 Unit V V A A V V mVp-p mVp-p mVp-p mA mW
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AM79761
PRELIMINARY
DVDD
DVDD
INPUT INPUT R INPUT R DVSS REFCLK and TTL Inputs DVSS High Speed Differential Input (RX) All Resistors 3.3K Current Limit
A
B
21560A-6
Figure 20.
Input Structures
AM79761
13
PRELIMINARY
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
AC CHARACTERISTICS
REFCLK T1 TXD[0:9] 10 Bit Data Data Valid T2 Data Valid
21560A-7
Data Valid
Figure 21.
Transmit Timing Waveforms
Table 21.
Symbol T1 Parameter Description
Transmit AC Characteristics
Test Conditions Min 1.5 Max -- Unit ns
Measured between the valid data TXD[0:9] Setup time to the rising level of TXD[0:9] to the 1.4 V point of edge of REFCLK REFCLK TXD[0:9] hold time after the rising edge of REFCLK TX rise and fall time Latency from rising edge of REFCLK to TXD0 appearing on TX20% to 80%, 75 load to VSS, Tested on a sample basis bc = Bit clocks ns = Nano second
T2 TSDR,TSDF
1.0 --
-- 300
ns ps
TLAT
11bc - 1ns
--
--
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AM79761
PRELIMINARY
AC CHARACTERISTICS (Continued)
T4 T3 RCLK
RCLKN T1 RXD[0:9] Data Valid Data Valid T2 Data Valid
21560A-8
Figure 22.
Receive Timing Waveform
Table 22.
Symbol T1 T2 Parameter Description Data or COM_DET Valid prior to RCLK/RCLKN rise Data or COM_DET Valid after RCLK or RCLKN rise
Receive AC Characteristics
Test Conditions Measured between the 1.4 V point of RCLK or RCLKN and a valid level of RXD[0:9]. All outputs driving 10 pF load. Min 3.0 2.0 Max -- -- Unit ns ns
T3
Deviation of RCLK rising edge to RCLKN rising edge delay Nominal delay is 10 bit times. from nominal. Tested on sample basis f
-500
500
ps
delay = ---------- T 3 10
baud
Deviation of RCLK, RCLKN frequency from nominal. T4
f REFCLK f RCLK = ------------------- T 4 2
RXD[0:9], COM_DET, RCLK, RCLKN rise and fall time Latency from RX to RXD[0:9] Data acquisition lock time @ 1.25 Gbps Receive Data Jitter Power
1 ------------------------------2 x BitTime
Whether or not locked to serial data
-1.0
1.0
%
TR, TF Rlat TLOCK Receive Data Jitter
Between VIL(MAX) and VIH(MIN), into 10 pf load. bc = Bit clock ns = Nano second 8B/10B IDLE pattern. Tested on a sample basis dBc, RMS for 10-12 Bit Error Ratio Tested on a sample basis
-- 15 bc + 2 ns
2.4 34 bc + 2 ns
ns --
--
2.0
s
100KHz
--
40
ps
PhaseNoise
AM79761
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PRELIMINARY
REFERENCE CLOCK REQUIREMENTS
TL REFCLK TH Vih (min) Vil (max)
21560A-9
Figure 23.
REFCLK Timing Waveform
Table 23.
Symbol Parameter Description
Reference Clock Requirements
Test Conditions Range over which both transmit and receive reference clocks on any link may be centered Min Max Units
FR
Frequency Range
123
127
MHz
FO
Frequency Offset
Maximum frequency offset between transmit and receive reference clocks on one link
-200
200
ppm
DC TRCR,TRCF
REFCLK duty cycle REFCLK rise and fall time
Measured at 1.5 V Between VIL(MAX) and VIH(MIN)
30 --
70 1.0
% ns
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AM79761
PRELIMINARY
MEASUREMENTS
Serial Input Rise and Fall Time 80% 20% Tr Tf Tr Tf TTL Input and Output Rise and Fall Time Vih(min) Vil(max)
Receiver Input Eye Diagram Jitter Tolerance Task Mask Bit Time
Amplitude
Eye Width%
Parametric Test Load Circuit Serial Output Load TTL AC Output Load
Z0 = 75W
75 VDD - 2.0 V
10 pF
21560A-10
Figure 24.
Parametric Measurement Information
AM79761
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PRELIMINARY
MEASUREMENTS (Continued)
Random Jitter Measurement
BERT Pattern Generator
DATA DATA
125 MHz
Trigger
CLK = 1.25 GHz DATA = 00000 0000011111 11111
Digitizing Scope
125 MHz
AM79761 RJ
-K28.7 0011111000
-K28.7 0011111000
REFCLK TXD[0:9]
TX+ TX-
1.25 Gbps Single-Ended Measurement
Random jitter (RJ) measurements performed according to Fibre Channel 4.3 Annex A, Test Methods, Section A.4.4. Measure standard deviation of all 50% crossing points. Peak to peak RJ is 7 sigma of distribution.
Deterministic Jitter Measurement
BERT Pattern Generator
DATA PAT SYNC
125 MHz
Trigger
CLK = 1.25 GHz DATA = 00000 0000011111 11111
Digitizing Scope
125 MHz
AM79761 DJ
-K28.5 0011111010
TRIGGER DATA
K28.5 1100000101
REFCLK TXD[0:9]
TX+ TX-
1.25 Gbps Single-Ended Measurement
20 bit time 19 bit time 18 bit time 17 bit time 12 bit time 10 bit time 9 bit time 8 bit time 7 bit time 2 bit time
Deterministic jitter (DJ) measurements performed according to Fibre Channel 4.3 Annex A, Test Methods, Section A.4.3. Measure time of all the 50% points of all ten transitions. DJ is the range of the timing variation from expected.
21560A-11
Figure 25.
Transmitter Jitter Measurement Method
Transmitter Output Jitter Allocation Trj TDJ Serial data output random jitter (RMS) Serial data output deterministic jitter (p-p) RMS, tested on a sample basis (refer to Figure 8) Peak to peak, tested on a sample basis (refer to Figure 8) -- -- 20 100 ps ps
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AM79761
PRELIMINARY
THERMAL CONSIDERATIONS
The AM79761 is packaged in a 14-mm or a 10-mm conventional PQFP with an internal heat spreader. These
packages use an industry-standard EIAJ footprint, but have been enhanced to improve thermal dissipation. The construction of the packages are as shown in Figure 26.
Plastic Molding Compound
Copper Heat Spreader
Lead
Bond Wire
Die
21560A-12
Figure 26.
Package Cross Section
Table 24.
Symbol jc ca ca-100 ca-200 ca-400 ca-600 Description Thermal resistance from junction to case
Thermal Resistance
10 mm Value 10.0 50.8 41.2 36.9 31.8 27.8 14 mm Value 9.5 29 26.1 23.8 20.5 17.9 Units
oC/W oC/W oC/W oC/W oC/W oC/W
Thermal resistance from case to ambient in still air including conduction through the leads. Thermal resistance from case to ambient with 100 LFM airflow Thermal resistance from case to ambient with 200 LFM airflow Thermal resistance from case to ambient with 400 LFM airflow Thermal resistance from case to ambient with 600 LFM airflow
The AM79761 is designed to operate with a junction temperature up to 105oC. The user must guarantee that the temperature specification is not violated. With the Thermal Resistances shown above, the 10x10 PQFP can operate in still air ambient temperatures of
Notes: 1. 50oC=110oC-1W*(10oC/W+50.8oC/W) 2. 72oC=110oC-1W*(95oC/W+29oC/W)
50oC, while the 14x14 PQFP can operate in still air ambient temperatures of 72oC. If the ambient air temperature exceeds these limits then some form of cooling through a heatsink or an increase in airflow must be provided.
AM79761
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PRELIMINARY
PHYSICAL DIMENSIONS PDH064 64-Pin (measured in millimeters)
Trademarks Copyright (c) 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. GigaPHY is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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AM79761

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